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- 1 - samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2013 samsung electronics co., ltd. all rights reserved. rev. 0.0 jun. 2013 samsung confidential klmxgxxemx-b031 samsung emmc product family e.mmc 5.0 specification compatibility datasheet
- 2 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target revision history revision no. history draft date remark editor 0.0 1. initial issue jun. 26, 2013 target s.m.lee
table of contents - 3 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 1.0 product list............................................................................................................... ........................................... 4 2.0 key features......... ............... .............. .............. .............. .............. ........... ........... ......... .......................................... 4 3.0 package configurations ..................................................................................................... ............................ 5 3.1 153 ball pin configuration ...... .............. .............. .............. .............. .............. ........... .......... ...................................... 5 3.1.1 11.5mm x 13mm x 0.8mm package dimension.............. .................................................................... .............. 6 3.2 product architecture ....................................................................................................... ......................................... 7 4.0 e.mmc 5.0 feature .......................................................................................................... ............................................ 8 4.1 hs400 mode............... .............. .............. .............. .............. .............. .............. .............. ........................................... 8 5.0 technical notes ............................................................................................................ .............................................. 10 5.1 s/w agorithm ............................................................................................................... ........................................... 10 5.1.1 partition management ..................................................................................................... .................................. 10 5.1.1.1 boot area partition and rpmb area partition . ........................................................................... ................ 10 5.1.1.2 enhanced partition (area) .............................................................................................. ............................ 10 5.1.2 boot operation........................................................................................................... ........................................ 11 5.1.3 user density............................................................................................................. ......................................... 12 5.1.4 auto power saving mode................................................................................................... ............................... 12 5.1.5 performance.............................................................................................................. ........................................ 13 6.0 register value ............................................................................................................. ........................................ 14 6.1 ocr register ............................................................................................................... ........................................... 14 6.2 cid register ............................................................................................................... ............................................. 14 6.2.1 product name table (in cid register) ............ ......................................................................... .......................... 14 6.3 csd register............................................................................................................... ............................................ 15 6.4 extended csd register ... .............. .............. .............. .............. ........... ........... ............ ......... .................................... 16 7.0 ac parameter............................................................................................................... ......................................... 21 7.1 timing parameter ................ ........................................................................................... ......................................... 21 7.2 previous bus timing parameters for ddr52 and hs200 mode are defined by jedec st andard........... ............... 21 7.3 bus timing specification in hs400 mode ..................................................................................... .......................... 22 7.3.1 hs400 device input timing ................................................................................................ .............................. 22 7.3.2 hs400 device output timing............................................................................................... ............................. 23 7.4 bus signal levels.......................................................................................................... ............................................ 24 7.4.1 open-drain mode bus signal le vel......................................................................................... ............................ 24 7.4.2 push-pull mode bus signal leve l emmc ..................................................................................... ....................... 24 8.0 dc parameter ............................................................................................................... ........................................ 25 8.1 active power consumption during operation ....... ........................................................................... ........................ 25 8.2 standby power consumption in auto power saving mode and standby state..................................................... ... 25 8.3 sleep power consumption in sleep state........... ......................................................................... .......................... 25 8.4 supply voltage ............................................................................................................. ........................................... 25 8.5 bus signal line load....................................................................................................... ........................................ 26
- 4 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target introduction samsung emmc is an embedded mmc solution designed in a bga package form. emmc operation is identical to a mmc device and ther efore is a simple read and write to memory using mmc protocol v5.0 which is a industry standard. emmc consists of nand flash and a mmc controller. 3v supply volt age is required for the nand area (vddf or vcc) whereas 1.8v o r 3v dual supply voltage (vdd or vccq) is supported for the mmc controller. sams ung e?mmc supports 200mhz ddr ? up to 400mbps with bus widths of 8 bit in order to improve sequential bandwidth, espec ially sequential read performance. there are several advantages of using emmc. it is easy to use as the mmc interface allows easy integration with any microproce ssor with mmc host. any revision or amendment of nand is invisible to the host as the embedded mmc controller insulates nand technology from the ho st. this leads to faster product development as well as faster times to market. the embedded flash management software or ftl( flash transition layer) of emmc manages wear leveling, bad block management and ecc. the ftl supports all features of the samsung na nd flash and achieves optimal performance. 1.0 product list [table 1] product list 2.0 key features ?? embedded multimediacard ver. 5.0 compatible. detail description is referenced by jedec standard ?? samsung emmc supports features of emmc5.0 which are defined in jedec standard - supported features : packed command, cache, discard, sanitize, power off notification, data tag, partition types, context id, real time clock, dynamic device capacity, hs200 - non-supported features : large sector size (4kb) ? additional features of emmc5.0 : hs400 mode (200m hz ddr - up to 400mbps), field firmware update, device health report, sleep notification, secure removal type ? full backward compatibility with prev ious multimediacard system specification (1bit data bus, multi-emmc systems) ? data bus width : 1bit (default), 4bit and 8bit ? mmc i/f clock frequency : 0 ~ 200mhz mmc i/f boot frequency : 0 ~ 52mhz ? temperature : operation (-25 ? c ~ 85 ? c), storage without operation (-40 ? c ~ 85 ? c) ? power : interface power vdd(vccq) (1.70v ~ 1.95v or 2.7v ~ 3.6v) , memory power vddf(vcc) (2.7v ~ 3.6v) capacities emmc part id nand flash type user density (%) power system package size pin configuration 4 gb klm4g1yemd-b031 32gb x 1 91.0% - interface power : vdd (1.70v ~ 1.95v or 2.7v ~ 3.6v) - memory power : vddf (2.7v ~ 3.6v) 11.5mm x 13mm x 0.8mm 153fbga 8 gb klm8g1wemb-b031 64gb x 1 16 gb KLMAG2WEMB-B031 64gb x 2
- 5 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 3.0 package configurations 3.1 153 ball pin configuration [table 2] 153 ball information figure 1. 153-fbga ? clk : clock input ? data strobe : newly assigned pin for hs400 mode. data strobe is generated from e.mmc to host. in hs400 mode, read data and crc response are synchronized with data strobe. ? cmd : a bidirectional signal used for device initializa tion and command transfers. command operates in two modes, open-dr ain for initialization and push-pull for fast command transfer. ? dat0-7 : bidirectional data channels. it operates in push-pull mode. ? rst_n : h/w reset signal pin ? vddf(vcc) : supply voltage for flash memory ? vdd(vccq) : supply voltage for memory controller ? vddi : internal power node to stabilize r egulator output to controller core logics ? vss : ground connections pin no name a3 dat0 a4 dat1 a5 dat2 b2 dat3 b3 dat4 b4 dat5 b5 dat6 b6 dat7 k5 rstn c6 vdd m4 vdd n4 vdd p3 vdd p5 vdd e6 vddf f5 vddf j10 vddf k9 vddf c2 vddi m5 cmd h5 data strobe m6 clk j5 vss a6 vss c4 vss e7 vss g5 vss h10 vss k8 vss n2 vss n5 vss p4 vss p6 vss vss vddf vddf vss vss dat7 vdd vddf clk vss dat2 dat6 vddf vss rstn cmd vss vdd dat1 dat5 v ss vdd vdd vss dat4 vdd dat3 vss dat0 vdd i dnu dnu dnu dnu dnu nc dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu a b c d e f g h j k l m n p 1234567891011121314 vss rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu vss rfu rfu rfu dnu dnu dnu dnu dnu dnu dnu dnu dnu data strobe
- 6 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 3.1.1 11.5mm x 13mm x 0.8mm g package dimension 0.08 max 0.70 0.10 top view 11.50 0.10 #a1 13.00 0.10 #a1 index mark bottom view 0.22 0.05 14 1 42 765 3 89 11 1312 10 0.50 x 13 = 6.50 11.50 0.10 a b (datum a) 0 . 5 0 13.00 0.10 0 . 5 0 (datum b) 153- ? 0.30 0.05 0.2 m a b ? 3.25 a b c e d f h j l k n p g m 13.00 0.10 3.25 0.50 x 13 = 6.50 figure 2. 11.5mm x 13mm x 0.8mm package dimension
- 7 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 3.2 product architecture control signal data bus mmc controller v ddf core regulator core memory nand i/o block mmc i/o block logic block (required for 3.3v vdd) v dd reset vddi data strobe cmd dat[7:0] c reg clk - emmc consists of nand flash and controller. v dd (v ccq ) is for controller power and v ddf (v cc )is for flash power figure 3. emmc block diagram
- 8 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 4.0 e.mmc 5.0 feature 4.1 hs400 mode e.mmc5.0 product supports high speed ddr interface timing mode up to 400mb/s at 200mhz with 1.8v i/o supply. hs400 mode supports the following features : ? ?? ddr data sampling method ?? clk frequency up to 200mhz ddr ? up to 400mbps ?? only 8-bits bus width available ?? signaling levels of 1.8v ?? six selectable drive strength (refer to the table below) [table 3] i/o driver strength types note: 1) support of driver type-0 is default for hs200 & hs400 devi ce, while supporting driver types 1~5 are optional for hs200 & hs4 00 device. 2) it is being discussed in jedec and is not confirmed yet. it can be modified acco rding to jedec standard in the future. [table 4] device type values (ext_csd register : device_type [196]) note: 1) it is being discussed in jedec and is not confirmed yet. it can be modified acco rding to jedec standard in the future. ? [table 5] extended csd revisions (ext _csd register : ext_csd_rev [192]) note: 1) current emmc standard defined by jedec supports up to 0x06 fo r ext_csd_rev value, 0x07 is addi tionally assigned to support e .mmc5.0 product. it is being discussed in jedec and is not confirmed yet. it can be modified according to jedec standard in the future. driver type hs200 & hs400 support nominal impedance approximated driving capability compared to type-0 remark 0 default 50 ? x1 default driver type. supports up to 200mhz operation. 1 optional 33 ? x1.5 supports up to 200mhz operation. 2 optional 66 ? x0.75 the weakest driver that supports up to 200mhz operation. 3 optional 100 ? x0.5 for low noise and low emi systems. maximal operating frequency is decided by host design. 4 optional 40 ? x1.2 supports up to 200mhz ddr operation bit device type supportability 7 hs400 dual data rate e?mmc @ 200 mhz - 1.2v i/o not support 6 hs400 dual data rate e?mmc @ 200 mhz - 1.8v i/o support 5 hs200 single data rate e ?mmc @ 200 mhz - 1.2v i/o not support 4 hs200 single data rate e ?mmc @ 200 mhz - 1.8v i/o support 3 high-speed dual data rate e ?mmc @ 52mhz - 1.2v i/o not support 2 high-speed dual data rate e ?mmc @ 52mhz - 1.8v or 3v i/o support 1 high-speed e ?mmc @ 52mhz - at rated device voltage(s) support 0 high-speed e ?mmc @ 26mhz - at rated device voltage(s) support value timing interface ext_csd register value 255-8 reserved - 7 revision 1.7 (for mmc v5.0) 0x07 1) 6 revision 1.6 (for mmc v4.5, v4.51) - 5 revision 1.5 (for mmc v4.41) - 4 revision 1.4 (obsolete) - 3 revision 1.3 (for mmc v4.3) - 2 revision 1.2 (for mmc v4.2) - 1 revision 1.1 (for mmc v4.1) - 0 revision 1.0 (for mmc v4.0) -
- 9 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target [table 6] high speed timing values (ext _csd register : hs_timing [185]) note: 1) it is being discussed in jedec and is not confirmed yet. it can be modified acco rding to jedec standard in the future. value timing interface supportability 0x0 selecting backwards compatibility interface timing support 0x1 high speed support 0x2 hs200 support 0x3 hs400 support
- 10 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 5.0 technical notes 5.1 s/w agorithm 5.1.1 partition management the device initially consists of two boot part itions and rpmb partition and user data area. the user data area can be divided into four general purpose area partitions and user data area partition. each of the general p urpose area partitions and a section of user data area partition can be configured as enhanced partition. 5.1.1.1 boot area partition and rpmb area partition boot partition size & rpmb partition size are set by the following command sequence : [table 7] setting sequence of boot area part ition size and rpmb area partition size boot partition size is calculated as (128kb * boot_size_mult) the size of boot area partition 1 and 2 can not be set independently. it is set as same value. rpmb partition size is calculated as (128kb * rpmb_size_mult). in rpmb partition, cmd 0, 6, 8, 12, 13, 15, 18, 23, 25 are admitted. access size of rpmb partit ion is defined as the below: [table 8] rel_wr_sec_c value for write operation on rpmb partition any undefined set of parameters or sequence of commands results in failure access. if the failure is in data programming case, the data is not programmed. and if the failure occurs in data read case, the read d ata is ?0x00?. 5.1.1.2 enhanced partition (area) samsung emmc adopts enhanced user data area as slc mode. theref ore when master adopts some portion as enhanced user data area in user data area, that area occupies triple size of original set up size. ( ex> if master set 1mb for enhanced mode, total 3mb user da ta area is needed to gener- ate 1mb enhanced area) max enhanced user data area size is defined as (max_enh_si ze_mult x hc_wp_grp_size x hc_erase_grp_size x 512kbytes) function command description partition size change mode cmd62(0xefac62ec) enter the partition size change mode partition size set mode cmd62(0x00cbaea7) partition size setting mode set boot partition size cmd62(boot_size_mult) boot partition size value set rpmb partition size cmd62(rpmb_size_mult) rpmb partition size value f/w re-partition is executed in this step. power cycle rel_wr_sec_c description rel_wr_sec_c = 1 access sizes 256b and 512b supported to rpmb partition rel_wr_sec_c > 1 access sizes up to rel_wr_sec_c * 512b supported to rpmb partition with 256b granularity
- 11 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 5.1.2 boot operation device supports not only boot mode but also alternative boot m ode. device supports high speed timing and dual data rate during boot. figure 4. embedded multimediacard state diagram (boot mode) figure 5. embedded multimediacard state diagram (alternative boot mode) [table 9] boot ack, boot data and initialization time note: 1) this initialization time includes partition setting, pl ease refer to ini_timeout_ap in 6.4 extended csd register. normal initialization time (without partition setting) is completed within 1sec timing factor value (1) boot ack time < 50 ms (2) boot data time < 100 ms (3) initialization time 1) < 3 secs se se 010 512bytes +crc clk cmd dat[0] cmd1 resp cmd2 resp boot terminated min 8 cloks + 48 clocks = 56 clocks required from cmd signal high to next mmc command. (1) (2) *(1) boot ack time (2) boot data time se se 010 512bytes +crc clk cmd dat[0] cmd1 resp cmd2 cmd0 1 cmd0 reset min74 clocks required after power is stable to start boot command *(1) boot ack time (2) boot data time (3) cmd1 time *cmd0 with argument 0xfffffffa (1) (2) boot terminated cmd1 (3)
- 12 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 5.1.3 user density total user density depends on device type. for example, 32mb in the slc mode requires 96mb in tlc. this results in decreasing of user density [table 10] capacity according to partition [table 11] maximum enhanced partition size [table 12] user density size 5.1.4 auto power saving mode if host does not issue any command during a certain duration (1ms ), after previously issued comm and is completed, the device en ters "power saving mode" to reduce power consumption. at this time, commands arriving at the device while it is in power saving mode will be serviced in normal fashion [table 13] auto power saving mode enter and exit [table 14] auto power saving mode and sleep mode boot partition 1 boot partition 2 rpmb 4,8 gb default. 4,096kb 4,096kb 512kb max. 4,096kb 4,096kb 4,096kb 16 gb default. 4,096kb 4,096kb 4,096kb max. 4,096kb 4,096kb 4,096kb device max. enhanced partition size 4 gb tbd 8 gb tbd 16 gb tbd device user density size 4 gb 3,909,091,328 bytes 8 gb 7,818,182,656 bytes 16 gb 15,634,268,160 bytes mode enter condition escape condition auto power saving mode when previous operation which came from host is completed and no com- mand is issued during a certain time. if host issues any command auto power saving mode sleep mode nand power on off gotosleep time < 1ms < 1ms 4 3 2 1 user density enhanced user data area 4 general purpose partitions (gpp) rpmb boot partition #1
- 13 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 5.1.5 performance [table 15] performance * test / estimation condition : bus width x8, 200mhz ddr, 512kb data transfer, w/o file system overhead density sequential read (mb/s) sequential write (mb/s) 4 gb 90 6 8 gb 16 gb 170 11
- 14 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 6.0 register value 6.1 ocr register the 32-bit operation conditions register stor es the vdd voltage profile of the emmc. in addition, this register includes a sta tus information bit. this status bit is set if the emmc power up procedure has been finis hed. the ocr register shall be implemented by all emmcs. [table 16] ocr register note : 1) this bit is set to low if the emmc has not finished the power up routine 2) the voltage for internal flash memory(vddf) shoul d be 2.7-3.6v regardless of ocr register value. 6.2 cid register [table 17] cid register note : 1),4),5) description are same as e.mmc jedec standard 2) prv is composed of the revision count of controller and the revision count of f/w patch 3) a 32 bits unsigned binary integer. (random number) 6.2.1 product name table (in cid register) [table 18] product name table ocr bit vdd voltage window 2 register value [6:0] reserved 00 00000b [7] 1.70 - 1.95 1b [14:8] 2.0-2.6 000 0000b [23:15] 2.7-3.6 1 1111 1111b [28:24] reserved 0 0000b [30:29] access mode 00b (byte mode) 10b (sector mode) -[ *higher than 2gb only] [31] emmc power up status bit (busy) 1 name field width cid-slice cid value manufacturer id mid 8 [127:120] 0x15 reserved 6 [119:114] --- card/bga cbx 2 [113:112] 01 oem/application id oid 8 [111:104] --- 1 product name pnm 48 [103:56] see product name table product revision prv 8 [55:48] --- 2 product serial number psn 32 [47:16] --- 3 manufacturing date mdt 8 [15:8] --- 4 crc7 checksum crc 7 [7:1] --- 5 not used, always ?1? - 1 [0:0] --- part number density product name in cid register (pnm) klm4g1yemd-b031 4 gb tbd klm8g1wemb-b031 8 gb tbd KLMAG2WEMB-B031 16 gb tbd
- 15 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 6.3 csd register the card-specific data register provides information on how to access the emmc contents. the csd defines the data format, erro r correction type, max - imum data access time, data transfer speed, whether the dsr regist er can be used etc. the programmable part of the register (en tries marked by w or e, see below) can be changed by cmd27. the type of t he entries in the table below is coded as follows: r : read only w: one time programmable and not readable. r/w: one time programmable and readable. w/e : multiple writable with value kept after power fa ilure, h/w reset assertion and any cmd0 reset and not readable. r/w/e: multiple writable with value kept after power failure, h/w reset assertion and any cmd0 reset and readable. r/w/c_p: writable after value cleared by power failure and hw/ rest assertion (the value not cleared by cmd0 reset) and readabl e. r/w/e_p: multiple writable with value reset after power failure, h/w reset assertion and any cmd0 reset and readable. w/e/_p: multiple wtitable with value reset after power fail ure, h/w reset assertion and any cmd0 reset and not readable. [table 19] csd register name field width cell type csd-slice csd value 4 gb 8 gb 16 gb csd structure csd_structure 2 r [127:126] 0x03 system specification version spec_vers 4 r [125:122] 0x04 reserved - 2 r [121:120] - data read access-time 1 taac 8 r [119:112] 0x27 data read access-time 2 in clk cycles (nsac*100) nsac 8 r [111:104] 0x01 max. bus clock frequency tran_speed 8 r [103:96] 0x32 device command classes ccc 12 r [95:84] 0xf5 max. read data block length read_bl_len 4 r [83:80] 0x09 partial blocks for read allowed read_bl_partial 1 r [79:79] 0x00 write block misalignment write_blk_misalign 1 r [78:78] 0x00 read block misalignment read_blk_misalign 1 r [77:77] 0x00 dsr implemented dsr_imp 1 r [76:76] 0x00 reserved - 2 r [75:74] - device size c_size 12 r [73:62] 0xfff max. read current @ vdd min vdd_r_curr_min 3 r [61:59] 0x06 max. read current @ vdd max vdd_r_curr_max 3 r [58:56] 0x06 max. write current @ vdd min vdd_w_curr_min 3 r [55:53] 0x06 max. write current @ vdd max vdd_w_curr_max 3 r [52:50] 0x06 device size multiplier c_size_mult 3 r [49:47] 0x07 erase group size erase_grp_size 5 r [46:42] 0x1f erase group size multiplier erase_grp_mult 5 r [41:37] 0x1f write protect group size wp_grp_size 5 r [36:32] 0x0f write protect group enable wp_grp_enable 1 r [31:31] 0x01 manufacturer default ecc default_ecc 2 r [30:29] 0x00 write speed factor r2w_factor 3 r [28:26] 0x03 0x04 max. write data block length write_bl_len 4 r [25:22] 0x09 partial blocks for write allowed write_bl_partial 1 r [21:21] 0x00 reserved - 4 r [20:17] - content protection application content_prot_app 1 r [16:16] 0x00 file format group file_format_grp 1 r/w [15:15] 0x00 copy flag (otp) copy 1 r/w [14:14] 0x01 permanent write protection perm_write_protect 1 r/w [13:13] 0x00 temporary write protection tmp_write_protect 1 r/w/e [12:12] 0x00 file format file_format 2 r/w [11:10] 0x00 ecc code ecc 2 r/w/e [9:8] 0x00 crc crc 7 r/w/e [7:1] - not used, always?1? - 1 ? [0:0] -
- 16 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 6.4 extended csd register the extended csd register defines the emmc pr operties and selected modes. it is 512 bytes long. the most significant 320 bytes are the properties segment, which defines the emmc capabilities and cannot be modified by the h ost. the lower 192 bytes are the modes segment, which defines the configuration the emmc is working in. these modes can be changed by the host by means of the switch command. r : read only w: one time programmable and not readable. r/w: one time programmable and readable. w/e : multiple writable with value kept after power fa ilure, h/w reset assertion and any cmd0 reset and not readable. r/w/e: multiple writable with value kept after power failure, h/w reset assertion and any cmd0 reset and readable. r/w/c_p: writable after value cleared by power failure and hw/ rest assertion (the value not cleared by cmd0 reset) and readabl e. r/w/e_p: multiple writable with value reset after power failure, h/w reset assertion and any cmd0 reset and readable. w/e/_p: multiple wtitable with value reset after power fail ure, h/w reset assertion and any cmd0 reset and not readable [table 20] extended csd register name field size (bytes) cell type csd-slice csd value 4 gb 8 gb 16 gb properties segment reserved 1 6 - [511:506] - extended security commands error ext_security_err 1 r [505] 0x00 supported command sets s_cmd_set 1 r [504] 0x01 hpi features hpi_features 1 r [503] 0x01 background operations support bkops_support 1 r [502] 0x01 max packed read commands max_packed_reads 1 r [501] 0x3f max packed write commands max_packed_writes 1 r [500] 0x3f data tag support data_tag_support 1 r [499] 0x01 tag unit size tag_unit_size 1 r [498] 0x04 tag resources size tag_res_size 1 r [497] 0x00 context management capabilities context_capabilities 1 r [496] 0x05 large unit size large_unit_size_m1 1 r [495] 0x07 extended partitions attribute support ext_support 1 r [494] 0x03 supported modes supported_modes 1 r [493] 0x01 ffu features ffu_features 1 r [492] 0x00 operation codes timeout operat ion_code_timeout 1 r [491] 0x00 ffu argument ffu_arg 4 r [490:487] 0x00 reserved 1 181 - [486:306] - number of received sectors number_of_received_ sectors 4 r [305:302] 0x00 vendor proprietary health report vendor_proprietary_ health_report 32 r [301:270] 0x00 device life time estimation type b device_life_time_est_ typ_b 1 r [269] 0x01 device life time estimation type a device_life_time_est_ typ_a 1 r [268] 0x01 pre eol information pre_eol_info 1 r [267] 0x01 optimal read size optimal_read_size 1 r [266] 0x00 optimal write size optimal_write_size 1 r [265] tbd optimal trim unit size optimal_trim_unit_size 1 r [264] 0x01 device version device_version 2 r [263:262] 0x00 firmware version firmware_version 8 r [261:254] fw patch ver. power class for 200mhz, ddr at vcc=3.6v pwr_cl_ddr_200_360 1 r [253] 0x00 cache size cache_size 4 r [252:249] 0x00010000 generic cmd6 timeout generic_cmd6_time 1 r [248] 0x0a
- 17 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target power off notification(long) timeout power_off_long_time 1 r [247] 0x3c background operations status bkops_status 1 r [246] 0x00 number of correctly programmed sectors correctly_prg_sectors _num 4 r [245:242] 0x00 1st initialization time after partit ioning ini_timeout_ap 1 r [241] 0x1e reserved 1 1 - [240] - power class for 52mhz, ddr at vcc = 3.6v pwr_cl_ddr_52_360 1 r [239] 0x00 power class for 52mhz, ddr at vcc = 1.95v pwr_cl_ddr_52_195 1 r [238] 0x00 power class for 200mhz at vccq = 1.95v, vcc = 3.6v pwr_cl_200_195 1 r [237] 0x00 power class for 200mhz, at vccq = 1.3v, vcc = 3.6v pwr_cl_200_130 1 r [236] 0x00 minimum write performance for 8bit at 52mhz in ddr mode min_perf_ddr_w_8_52 1 r [235] 0x00 minimum read performance for 8bit at 52mhz in ddr mode min_perf_ddr_r_8_52 1 r [234] 0x00 reserved 1 1 - [233] - trim multiplier trim_mult 1 r [232] 0x02 secure feature support sec_feature_support 1 r [231] 0x55 secure erase multiplier sec_erase_mult 1 r [230] 0x1b secure trim multiplier sec_trim_mult 1 r [229] 0x11 boot information boot_info 1 r [228] 0x07 reserved 1 1 - [227] - boot partition size boot_size_mult 1 r [226] 0x20 access size acc_size 1 r [225] tbd high-capacity erase unit size hc_erase_grp_size 1 r [224] 0x01 high-capacity erase timeout er ase_timeout_mult 1 r [223] 0x01 reliable write sector count rel_wr_sec_c 1 r [222] 0x01 high-capacity write protect group si ze hc_wp_grp_size 1 r [221] 0x10 sleep current (vcc) s_c_vcc 1 r [220] 0x07 sleep current (vccq) s_c_vccq 1 r [219] 0x07 product state awareness timeout production_state_ awareness_timeout 1 r [218] 0x00 sleep/awake timeout s_a_timeout 1 r [217] 0x11 sleep notification timeout sleep_notification_time 1 r [216] 0x07 sector count sec_count 4 r [215:212] 0x748000 0xe90000 0x1d1f000 reserved 1 1 - [211] - minimum write performance for 8bit at 52mhz min_perf_w_8_52 1 r [210] 0x00 minimum read performance for 8bit at 52mhz min_perf_r_8_52 1 r [209] 0x00 minimum write performance for 8bit at 26mhz, for 4bit at 52mhz min_perf_w_8_26_4_52 1 r [208] 0x00 minimum read performance for 8bit at 26mhz, for 4bit at 52mhz min_perf_r_8_26_4_52 1 r [207] 0x00 minimum write performance for 4bit at 26mhz min_perf_w_4_26 1 r [206] 0x00 minimum read performance for 4bit at 26mhz min_perf_r_4_26 1 r [205] 0x00 reserved 1 1 - [204] - power class for 26mhz at 3.6v 1 r pwr_cl_26_360 1 r [203] 0x00
- 18 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target power class for 52mhz at 3.6v 1 r pwr_cl_52_360 1 r [202] 0x00 power class for 26mhz at 1.95v 1 r pwr_cl_26_195 1 r [201] 0x00 power class for 52mhz at 1.95v 1 r pwr_cl_52_195 1 r [200] 0x00 partition switching timing partition_switch_time 1 r [199] 0x01 out-of-interrupt busy timing out_ of_interrupt_time 1 r [198] 0x05 i/o driver strength csd structure version driver_strength 1 r [197] 0x1f device type device_type 1 r [196] 0x57 reserved 1 1 - [195] - csd structure version csd_structure 1 r [194] 0x02 reserved 1 1 - [193] - extended csd revision ext_csd_rev 1 r [192] 0x07 modes segment command set cmd_set 1 r/w/e_p [191] 0x00 reserved 1 1 - [190] - command set revision cmd_set_rev 1 r [189] 0x00 reserved 1 1 - [188] - power class power_class 1 r/w/e_p [187] 0x00 reserved 1 1 - [186] - high-speed interface timing hs_timing 1 r/w/e_p [185] 0x00 reserved 1 1 - [184] - bus width mode bus_width 1 w/e_p [183] 0x00 reserved 1 1 - [182] - erased memory content erased_mem_cont 1 r [181] 0x00 reserved 1 1 - [180] - partition configuration partition_config 1 r/w/e & r/w/e_p [179] 0x00 boot config protection boot_config_prot 1 r/w & r/w/c_p [178] 0x00 boot bus conditions boot_bus_conditions 1 r/w/e [177] 0x00 reserved 1 1 - [176] - high-density erase group definition erase_group_def 1 r/w/e_p [175] 0x00 boot write protection status regist ers boot_wp_status 1 r [174] 0x00 boot area write protection register boot_wp 1 r/w & r/w/c_p [173] 0x00 reserved 1 1 - [172] - user area write protection register user_wp 1 r/w, r/w/c_p &r/w/ e_p [171] 0x00 reserved 1 1 - [170] - fw configuration fw_config 1 r/w [169] 0x00 rpmb size rpmb_size_mult 1 r [168] 0x04 0x20 write reliability setting register wr_rel_set 1 r/w [167] 0x1f write reliability parameter register wr_rel_param 1 r [166] 0x04 start sanitize operation sanitize_start 1 w/e_p [165] 0x00 manually start background operations bkops_start 1 w/e_p [164] 0x00 enable background operations handshake bkops_en 1 r/w [163] 0x00 h/w reset function rst_n_function 1 r/w [162] 0x00 hpi management hpi_mgmt 1 r/w/e_p [161] 0x00
- 19 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target note : 1) reserved bits should be read as ?0.? partitioning support partitioning_support 1 r [160] 0x07 max enhanced area size max_enh_size_mult 3 r [159:157] tbd partitions attribute partitions_attribute 1 r/w [156] 0x00 partitioning setting partition_setting_ completed 1 r/w [155] 0x00 general purpose partition size gp_size_mult 12 r/w [154:143] 0x00 enhanced user data area size enh_size_mult 3 r/w [142:140] 0x00 enhanced user data start address enh_start_addr 4 r/w [139:136] 0x00 reserved 1 1 - [135] - bad block management mode sec_bad_blk_mgmnt 1 r/w [134] 0x00 production state awareness production_state_ awareness 1 r/w/e [133] 0x00 package case temperature is controlled tcase_support 1 w/e_p [132] 0x00 periodic wake-up periodic_wakeup 1 r/w/e [131] 0x00 program cid/csd in ddr mode support program_cid_csd_ddr_s upport 1 r [130] 0x01 reserved 1 64 - [129:66] - optimized features optimized_features 2 r [65:64] 0x0f native sector size native_sector_size 1 r [63] 0x00 sector size emulation use_native_sector 1 r/w [62] 0x00 sector size data_sector_size 1 r [61] 0x00 1st initialization after disabling sector size emulation ini_timeout_emu 1 r [60] 0x00 class 6 commands control class_6_ctrl 1 r/w/e_p [59] 0x00 number of addressed group to be released dyncap_needed 1 r [58] 0x00 exception events control exception_events_ctrl 2 r/w/e_p [57:56] 0x00 exception events status exception_events_statu s 2 r [55:54] 0x00 extended partitions attribute ext_partitions_attribute 2 r/w [53:52] 0x00 context configuration context_conf 15 r/w/e_p [51:37] 0x00 packed command status packed_command_status 1 r [36] 0x00 packed command failure index packed_failure_index 1 r [35] 0x00 power off notification power_off_notification 1 r/w/e_p [34] 0x00 control to turn the cache on/off cache_ctrl 1 r/w/e_p [33] 0x00 flushing of the cache flush_cache 1 w/e_p [32] 0x00 reserved 1 1 - [31] - mode config mode_config 1 r/w/e_p [30] 0x00 mode operation codes mode_operation_codes 1 w/e_p [29] 0x00 reserved 1 2 - [28:27] - ffu status ffu_status 1 r [26] 0x00 pre loading data size pre_loading_data_size 4 r/w/e_p [25:22] 0x00 max pre loading data size max_pre_loading_data_ size 4 r [21:18] 0x00 product state awareness enablement product_state_awarene ss_enablement 1 r/w/e & r [17] 0x00 secure removal type secure_removal_type 1 r/w & r [16] 0x09 reserved 1 16 - [15:0] -
- 20 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 7.0 ac parameter 7.1 timing parameter [table 21] timing parameter note: 1) normal initialization time without partition setting 2) initialization time after partition setting, refer to ini_timeout_ap in 6.4 ext_csd register 3) be advised timeout values specified in table above are for testing purposes under sa msung test pattern only and actual timeo ut situations may vary 4) exception_event may occur and the actual ti meout values may vary due to user environment 7.2 previous bus timing parameters for ddr52 and hs200 mode are defined by jedec standard timing paramter max. value unit initialization time (tinit) normal 1) 1s after partition setting 2) 3s read timeout 100 ms write timeout 350 ms erase timeout 20 ms force erase timeout 3min secure erase timeout 8s secure trim step1 timeout 5s secure trim step2 timeout 3s trim timeout 600 ms partition switching timeout (after init) 1 ms power off notification (short) timeout 100 ms power off notification (long) timeout 600 ms
- 21 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 7.3 bus timing specification in hs400 mode 7.3.1 hs400 device input timing figure 6. hs400 device input timing note: 1) t isu and t ih are measured at v il (max.) and v ih (min). 2) v ih denotes v ih (min.) and v il denotes v il (max.) [table 22] hs400 device input timing note : 1) it is being discussed in jedec and is not confirmed yet. it can be modified according to jedec standard in the future. parameter symbol min max. unit input clk cycle time data transfer mode t period 5-ns clock rising / falling time t tlh , t thl - 0.1t period (=0.5) ns clock duty cycle 46 54 % input dat (referenced to clk) input set-up time tisuddr 0.4 ns input hold time tihddr 0.4 ns vccq vss vss vccq dat[7-0] input clock input valid window valid window t isuddr t ihddr t isuddr t ihddr v il v ih v il v ih t tlh t thl v il v ih v t t period
- 22 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 7.3.2 hs400 device output timing data strobe is used to read data (data read and crc status respons e read) in hs400 mode. the device output value of data strobe is ?high-z? when the device is not in outputting data(data read, crc status re sponse). data strobe is toggled only during data read period. figure 7. hs400 device output timing note: v oh denotes v oh (min.) and v ol denotes v ol (max.). [table 23] hs400 device output timing note : 1) it is being discussed in jedec and is not confirmed yet. it can be modified according to jedec standard in the future. parameter symbol min max. unit output data strobe cycle time data transfer mode t period 5-ns clock rising/falling time t tlh , t thl - 0.16t period (=0.8) ns clock duty cycle 42 58 % output dat (referenced to data strobe) output hold skew trq 0.4 ns output hold time trqh 0.4 ns vccq vss vccq vss dat[7-0] output valid window valid window v oh v ol v oh v ol v oh v t v ol t period t tlh t rq t thl t rqh data strobe output
- 23 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 7.4 bus signal levels as the bus can be supplied with a vari able supply voltage, all signal levels are related to the supply voltage. 7.4.1 open-drain mode bus signal level [table 24] open-drain bus signal level note: 1) because voh depends on external resistanc e value (including outside the package), this value does not apply as device specif ication. host is responsible to choose the external pu ll-up and open drain resistance value to meet voh min value. 7.4.2 push-pull mode bus signal level emmc the device input and output voltages shall be with in the following specified ranges for any v dd of the allowed voltage range [table 25] push-pull signal level?high-voltage emmc [table 26] push-pull signal level?1.70 - 1.95 v ccq voltage range note: 1) 0.7*v ccq for mmc4.3 and older revisions. 2) 0.3*v ccq for mmc4.3 and older revisions. parameter symbol min max. unit conditions output high voltage v oh v dd - 0.2 -v 1) output low voltage v ol -0.3v i ol = 2 ma parameter symbol min max. unit conditions output high voltage v oh 0.75*v ccq -v i oh = -100 ua@v ccq min output low voltage v ol - 0.125*v ccq v i ol = 100 ua@v ccq min input high voltage v ih 0.625*v ccq v ccq + 0.3 v- input low voltage v il v ss - 0.3 0.25*v ccq v- parameter symbol min max. unit conditions output high voltage v oh v ccq - 0.45v -v i oh = -2ma output low voltage v ol - 0.45v v i ol = 2ma input high voltage v ih 0.65*v ccq 1) v ccq + 0.3 v- input low voltage v il v ss - 0.3 0.35*v ccq 2) v- v t input high level input low level output high level output low level undefined v dd v ih v oh v il v ss v ol
- 24 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 8.0 dc parameter 8.1 active power consumption during operation [table 27] active power consumption during operation * power measurement conditions: bus configuration =x8 @200mhz ddr * the measurement for max rms current is the aver age rms current consumption over a period of 100ms. 8.2 standby power consumption in auto power saving mode and standby state. [table 28] standby power consumption in auto power saving mode and standby state note: power measurement conditions: bu s configuration =x8, no clk *typical value is measured at vcc=3.3v, ta=25c. not 100% tested. 8.3 sleep power consum ption in sleep state [table 29] sleep power consumption in sleep state note: power measurement conditions: bu s configuration =x8, no clk 1) in auto power saving mode , nand power can not be turned off .however in sleep mode nand power can be turned off. if nand po wer is alive , nand power is same with that of the standby state. 8.4 supply voltage [table 30] supply voltage density nand type ctrl nand unit 4 gb 32 gb x 1 150 80 ma 8 gb 64 gb x 1 16 gb 64 gb x 2 130 density nand type ctrl nand unit 25 ? c(typ) 85 ? c 25 ? c(typ) 85 ? c 4 gb 32 gb x 1 tbd tbd 40 85 ua 8 gb 64 gb x 1 16 gb 64 gb x 2 50 135 density nand type ctrl nand unit 25 ? c(typ) 85 ? c 4 gb 32 gb x 1 tbd tbd 0 1) ua 8 gb 64 gb x 1 16 gb 64 gb x 2 item min max unit v dd (v ccq ) 1.70 (2.7) 1.95 (3.6) v v ddf (v cc )2.73.6v v ss -0.5 0.5 v
- 25 - if there is any other operation to implement in additi on to specification in the datasheet or jedec standard, please contact each branch office or headquarters of samsung electronics. datasheet emmc rev. 0.0 klmxgxxemx-b031 samsung confidential target 8.5 bus signal line load the total capacitance c l of each line of the emmc bus is the sum of the bus master capacitance c host , the bus capacitance c bus itself and the capac - itance c device of the emmc connected to this line: c l = c host + c bus + c device the sum of the host and bus capacitances should be under 20pf. [table 31] bus signal line load [table 32] capacitance and resistance for hs400 mode parameter symbol min typ. max unit remark pull-up resistance for cmd r cmd 4.7 100 kohm to prevent bus floating pull-up resistance for dat0-dat7 r dat 10 100 kohm to prevent bus floating internal pull up resistance dat1-dat7 r int 10 150 kohm to prevent unconnected lines floating single device capacitance c device 12 pf maximum signal line inductance 16 nh f pp <= 52 mhz parameter symbol min typ max unit remark bus signal line capacitance cl 13 pf single device single device capacitance c device 6pf pull-down resistance for data strobe r data strobe 10 100 kohm

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